|
課程名稱 |
專題研究
Special Project |
|
開課學期 |
111-1 |
|
授課對象 |
電子工程學研究所 |
|
授課教師 |
陳景然 |
|
課號 |
EEE7002 |
|
課程識別碼 |
943 M0030 |
|
班次 |
35 |
|
學分 |
1.0 |
|
全/半年 |
半年 |
|
必/選修 |
必修 |
|
上課時間 |
|
|
上課地點 |
|
|
備註 |
碩士班在學期間每學期必修。
限本系所學生(含輔系、雙修生)
總人數上限：50人 |
|
|
|
|
課程簡介影片 |
|
|
核心能力關聯 |
核心能力與課程規劃關聯圖 |
|
課程大綱
|
|
為確保您我的權利,請尊重智慧財產權及不得非法影印
|
|
課程概述 |
Logic synthesis is an automated process of generating logic circuits satisfying certain Boolean constraints and/or transforming logic circuits with respect to optimization objectives. It is an essential step in the design automation of VLSI systems and is crucial in extending the scalability of formal verification tools. This course introduces classic logic synthesis problems and solutions as well as some recent developments. |
|
課程目標 |
This course is intended to introduce Boolean algebra, Boolean function representation and manipulation, logic circuit optimization, circuit timing analysis, formal verification, and other topics. The students may learn useful Boolean reasoning techniques for various applications even beyond logic synthesis. |
|
課程要求 |
The prerequisite is the undergrad "Logic Design" course. Knowledge about data structures and programming would be helpful. |
|
預期每週課後學習時數 |
|
|
Office Hours |
|
|
指定閱讀 |
|
|
參考書目 |
* F. M. Brown. Boolean Reasoning: The Logic of Boolean Equations. Dover, 2003.
* S. Hassoun and T. Sasao. Logic Synthesis and Verification. Springer, 2001.
* G. D. Hachtel and F. Somenzi. Logic Synthesis and Verification Algorithms. Springer, 2006.
* W. Kunz and D. Stoffel. Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques. Springer, 1997. |
|
評量方式
(僅供參考) |
|
|